The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristor-based devices.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices has led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories; the circuitry used to store digital information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information.
Various SRAM cell designs based on NDR (Negative Differential Resistance) devices have been proposed in the past. These designs typically consist of at least two active elements, including an NDR device. The NDR device is important to the overall performance of this type of SRAM cell. A variety of NDR devices have been introduced ranging from a simple bipolar transistor to complicated quantum-effect devices. One advantage of the NDR-based cell is the potential of having a cell area smaller than 4T and 6T SRAM cells because of the smaller number of active devices and interconnections. Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. Some of these problems include: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for the cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to i slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
NDR devices including thyristors are also widely used in power switching applications because the current densities carried by such devices can be very high in their on state. Additionally, in a thin capacitively coupled thyristor (TCCT) device, a base region is capacitively coupled to a control port, such as a gate. This capacitive coupling enhances the switching of the thyristor between the blocking state and conducting state. An important aspect of a TCCT device is that the body of the thyristor is thin enough so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Because of this, many of the straightforward implementations of a thyristor in a bulk substrate cannot form a device sufficient to meet selected applications, such as those benefiting from a TCCT device.
One method to make a thyristor-based device is to form a vertical silicon pillar by first depositing a layer of silicon and then subsequently masking and etching the deposited silicon layer, leaving the pillar behind. However this method causes a number of manufacturing issues, including issues related to the forming of structures, such as planar MOSFET devices, after the formation of the thyristor. For example, it is extremely difficult to add STI (Shallow Trench Isolation) after the pillar etch since STI usually requires a chemical-mechanical polishing (CMP) step. Also, patterning used to form a mask, such as for photolithography, is difficult near such a pillar due to resist puddling. Additionally, angled implants used after the formation of the pillar may introduce shadowing problems, resulting in the pillar being implanted instead of the intended implantation of other devices near the thyristor. Implanting the pillar to form the thyristor, as well as masking horizontal devices near the pillar, such as source/drain regions of a MOSFET, is also challenging.
The above-mentioned and other difficulties associated with the formation of vertical thyristor-based devices have and continue to present challenges to the manufacture and implementation of such devices.
The present invention is directed to a thyristor-based memory cell that addresses the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device is manufactured having a thyristor structure that addresses the problems mentioned hereinabove. A transistor is formed in a semiconductor substrate having an upper surface. The transistor includes a gate over the upper surface and source/drain regions in the substrate below the upper surface. After forming the transistor, a thyristor is formed using one of the source/drain regions as a portion of the thyristor and extending over the upper surface. In this manner, the thyristor can be formed after the formation of the transistor and/or other circuit elements in the substrate.
In a more particular example embodiment of the present invention, a vertical TCCT device is formed over a semiconductor surface having a source drain region of a transistor formed therein, and a gate for the transistor formed thereon. First, an oxide is formed over the surface and the gate, and an opening is etched in the oxide over the source/drain region. Polysilicon is deposited in the opening and doped to form a first base region of the TCCT adjacent the source/drain region. The first base region is doped to a polarity opposite of the source/drain region, and the combination of the first base region and the source/drain region make up an end portion (e.g., anode or cathode) of the vertical TCCT. A second base region is formed on the first base region, and an emitter is formed on the second base region, the emitter and second base regions making up a second end portion of the TCCT and having an opposite polarity of the first end portion. A portion of the oxide adjacent the TCCT is removed and a thin capacitively coupled gate is formed in place of the oxide, adjacent one of the base regions and capacitively coupled to the base region.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.